Optoelectronic components such as lasers, optical amplifiers and photodetectors fabricated in semiconducting materials depend upon the reliable formation of low resistance ohmic contacts to semiconductor layers. To make such devices, non-planar structures such as mesas and ridges are often fabricated by etching through successive layers of various compositions. Aligning a narrow stripe contact over a mesa which is only 1 to 5 microns wide and running the entire length of the sample or wafer, (up to several centimeters), such as in the case of a laser, is a difficult task even with field alignment on the mask. Nonplanarity of the photoresist adds to the difficulty of alignment. Consequently, the process is inherently low yielding and unreliable. In addition, for device performance purposes it is paramount to minimize the parasitic resistances.
The self-aligned ohmic contact process used in silicon VLSI technology is very similar in result to the localized flood exposure process disclosed in this application, but is not amenable at this time to the fabrication of optoelectronic components such as laser diodes.
The metallization liftoff process routinely used in gallium arsenide MESFET technology, which is a version of the self-aligned process, may be used in the ohmic metal deposition step of the process of this invention. The planarization process is very similar, but it does not utilize localized flood exposure, not does it yield bare sidewalls, a salient feature of the process of this invention.